quiz

Pipelining

Overview of Pipelining

1. Which of the following stages is not a typical stage in a basic pipeline?

  • A) Fetch
  • B) Decode
  • C) Execute
  • D) Synchronize
D) Synchronize Explanation

2. What is a “stall” in the context of a pipelined computer?

  • A) A state where the CPU halts due to a power failure  
  • B) A situation where the pipeline must discard data and restart due to a program switching instructions
  • C) An interruption in the clock cycle that increases CPU throughput
  • D) A method to reduce energy consumption in the CPU  
B) A situation where the pipeline must discard data and restart due to a program switching instructions Explanation

3. What type of hazard occurs when a subsequent instruction needs data from a previous instruction that has not yet been completed?

  • A) Structural Hazard
  • B) Control Hazard
  • C) Data Hazard
  • D) Execution Hazard
C) Data Hazard Explanation

4. Which technique is used to handle control hazards caused by branch instructions?

  • A) Pipeline Stalling
  • B) Forwarding
  • C) Instruction Reordering
  • D) Branch Prediction
D) Branch Prediction Explanation

5. Which of the following is a data hazard where a write operation is performed before a read operation on the same data?

  • A) RAW (Read After Write)
  • B) WAR (Write After Read)
  • C) WAW (Write After Write)
  • D) RAR (Read After Read)
B) WAR (Write After Read) Explanation

6. In a 5-stage pipeline, the first instruction is an ADD, the second instruction is a LOAD that causes a 2-cycle data hazard stall, and the third instruction is a branch with a 1-cycle control hazard delay. How many clock cycles are needed to complete the execution of 5 instructions?

  • A) 8
  • B) 9
  • C) 10
  • D) 11
C) 10 Explanation

7. What technique involves providing an instruction with the result of a previous instruction before it is written back to the register file?

  • A) Pipeline Stalling
  • B) Forwarding (or Bypassing)
  • C) Branch Prediction
  • D) Instruction Reordering
B) Forwarding (or Bypassing) Explanation

8. what is the main reason for pipeline hazards?

  • A) Slow memory access  
  • B) Limited register availability  
  • C) Concurrent instruction execution  
  • D) Low clock speed  
C) Concurrent instruction execution   Explanation

9. In a pipelined processor, how many instructions can ideally be completed per clock cycle?

  • A) 0.5 instructions  
  • B) 1 instruction  
  • C) 2 instructions  
  • D) Depends on the number of pipeline stages  
B) 1 instruction Explanation

10. What is a pipeline “bubble” in a pipelined processor?

  • A) A delay caused by a stall
  • B) An additional instruction was added to the pipeline
  • C) Instruction execution  
  • D) Instruction processing speed  
B) A delay caused by a stall Explanation

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