The MESI protocol (Modified, Exclusive, Shared, Invalid) maintains cache coherency, ensuring that all CPU cores have the most recent value of shared data. The protocol uses four states to manage the status of a cache line (a block of memory) in each processor’s cache:
- Modified (M):
- The cache line is present only in the current cache and has been modified (written to) by the processor.
- The data is inconsistent with the main memory (it is the only valid copy).
- Before this cache line can be read by another processor or written back to memory, it must be written (or “flushed”) to the main memory to update the memory with the new value.
- Exclusive (E):
- The cache line is present only in the current cache and matches the main memory.
- No other cache has a copy of this data.
- The data can be modified without notifying other caches, after which it will transition to the “Modified” state.
- Shared (S):
- The cache line is present in multiple caches, and all copies are identical to the main memory.
- The data is not modified in any cache.
- Any processor can read the data, but if a write operation is needed, the cache line must transition to either a “Modified” or “Invalid” state, depending on the specific implementation.
- Invalid (I):
- The cache line is not valid; it either has no data or its data is stale.
- The cache cannot use this data until it is updated with a valid copy, either from another cache or from main memory.